The invention relates generally to fault-detection technology based on error correction code ("ECC") technology employed in correcting errors in data read from a disk of a disk drive. More specifically, it relates to an ECC integrated circuit ("IC") having the capability for built-in self testing.
In each of various processes for mass production of ICs, a substantial number of tests are conducted at various stages of the overall process to weed out defective structures. There are wafer-level tests that weed out whole wafers that appear unlikely to produce good die. There are die-level tests conducted on the die prior to separation from the wafer to weed out die that appear unlikely to produce good ICs. There are "final" tests conducted after the die are packaged to weed out defective ICs.
There are various test architectures relevant here. One such architecture is referred to as"Scan." Another such architecture is referred to as "Built-In Self Test" or "BIST." Another such architecture is referred to as "Scan BIST."
The Scan architecture involves allocating some of the die area of the IC to the testing function, and also providing external test equipment to carry out a test procedure. In an IC that is compatible with the Scan architecture, various registers and switches are added or modified to support the Scan test. When the chip is operated in a test mode, the switches connect the registers and blocks under test into a chain. An externally generated test pattern is supplied to an input of the chain, and a response on an output of the chain is compared to a known "correct" response. If a block in the chain has a "stuck-at fault," the output response will be different from the correct response.
Although Scan is good at detecting "stuck-at" faults, it is not very good at detecting "timing faults" because it cannot be run "at speed." Scan requires an external tester to generate and supply the test pattern to the chip and evaluate the response of the chip. However, the external tester generally runs slower than the clock speed of the chip and, therefore, prevents the test from being run at speed.
Moreover, Scan is costly to implement. With each switch that is added to the chip and with each register that is modified or added, this increases overhead and accordingly the cost of the chip is increased. The cost increase typically results from an increase in die area and an impact on the design schedule. Scan can increase the cost of a chip by 5% to 20%.
The BIST architecture generally involves the construction of a test pattern generator ("TPG") and a test answer evaluator ("TAE") on a chip. The TPG generates test patterns for blocks under test and the TAE evaluates the responses of the blocks to the test patterns. Although good at detecting timing faults, BIST increases cost of the chip by 10% to 20%.
Scan BIST is a combination of Scan and BIST. Switches, registers, a TPG and a TAE are all constructed on a chip. However, the increase in cost is the greatest among the three test architectures, typically between 10% and 25%.
With all three architectures, the cost of a chip is increased disproportionately as the level of circuit integration is increased. Thus, the increased cost can become quite significant in highly integrated, submicron chips.
Cost can be reduced by reducing the fault coverage on a chip. The number of signals in the test pattern for BIST and Scan BIST can be reduced, and the number of registers and switches for Scan and Scan BIST can be reduced. However, the reduction in overhead comes at a price: an increase in the likelihood that a fault will not be detected.
In the disk drive industry, timing faults are especially problematic. Disk drive manufacturers are continually striving to pack more and more circuits into a single integrated circuit disk controller chip. The assignee of this invention has developed a very powerful disk controller chip embodying inventions disclosed and claimed in certain patent applications including application Ser. No. 08/436,521, filed May 8, 1995, titled "DISK DRIVE WITH ERROR CODE EMBEDDED SECTOR IDENTIFICATION," Docket No. K35A0241!, the disclosure of which is hereby incorporated by reference herein; this application is hereinafter referred to as the "Incorporated ECC Disclosure." The Incorporated ECC Disclosure discloses in detail the construction and operation of circuitry and firmware that provides for two types of error detection, one type being performed as a function within an error correction process, and a second type being performed to verify the result of performing an error correction to reduce the risk of a miscorrection. The error correction process involves interleaved codewords in a first Reed-Solomon code. The process of detecting miscorrections involves a codeword in a second Reed-Solomon code. Some systems employ Cyclic Redundancy Codes (CRC) for detecting miscorrections, rather than a Reed-Solomon error detection code.
As this level of integration continues to increase, timing faults will become more prominent on the disk controller chips. Here lies the problem. The disk drive manufacturers cannot afford to mount defective chips to disk controller boards or, worse yet, sell disk drives containing defective disk controller chips and disk controller boards to customers. However, the disk drive manufacturers also cannot afford to increase the cost in order to test for timing faults in the highly integrated, submicron disk drive controllers. At the present level of circuit integration, disk controller chips are not tested completely for timing faults due to the significant cost of BIST and Scan BIST. However, as the level of chip integration is increased, and the chances for a fault occurring in a disk controller chip are also increased, the reduction in fault coverage will become unacceptable.
A need exists for a test that is capable of detecting timing faults in a highly integrated chip without significantly increasing the cost of the chip.